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Memory sparing uses a spare online bank to provide DIMM
fail-over capabilities when a pre-defined threshold of single-bit
correctable errors is reached. The pre-defined threshold is
set in BIOS and cannot be change by the user.
DIMM capacity and configuration requirements:
- Memory is 4-way interleaved and as a result the DIMMs
must be installed in banks consisting of 4 DIMMs per bank.
- The DIMMs in a bank must be of the same capacity, manufacturer,
and have the same SPD characteristics. No mixing of memory
DIMMs is allowed.
- Bank #1 and bank #2 are defined as the "Active banks".
Bank #3 is defined as the spare bank. For memory sparing
to function, DIMMs must be installed in the active and spare
banks.
The table below lists the configuration for memory sparing:
| |
Bank #1(Active Bank) |
Bank #2(Active Bank) |
Bank #3(Spare Bank) |
|
4 DIMM configuration
|
Installed |
Not installed |
Not installed |
Not Available |
8 DIMM configuration
|
Installed |
Not installed |
Installed |
Available |
| 12 DIMM configuration |
Installed |
Installed |
Installed |
Available |
NOTE. The spare bank will be removed from the memory pool
and held as a spare; for instance, if 12 x 1 GB DIMMs are
installed, only 8 GB of that 12 GB is available for use
by the operating system.
How memory sparing works:
In normal mode of operation, the system reads/writes memory
data to the active bank(s) (bank #1 and bank #2). The system
does not read/write memory data to the spare bank (bank
#3). Bank #3 does not store memory data before memory data
sparing begins. The memory sparing function moves memory
data from the bank registering errors to the spare bank,
if the correctable error count exceeds the threshold value.
After moving the memory data, the system de-activates the
bank registering errors and records an error log. Further,
the system status LED will blink.
Memory sparing does not recover non-correctable errors.
Therefore, if the system detects non-correctable errors,
the system will assert fatal error status, and the system
will halt.
The system is not able to use memory mirroring and memory
sparing concurrently.
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